FIR Digital Filter on Lattice FPGA
This uses Lattice Semiconductors IspDesign Expert (A free download, followed by
a free renewable 6 month license). All you have to figure out is the JTAG
interface. Ours is from the Vantis design kit, before they were bought out by
Lattice. The Finite Impulse Response filter has a guaranteed linear phase (for
symmetrical coefficients), so no delay equalisation is required, as it is for
other types. It's also not prone to going into wild oscillations as the IIR
type apparantly is. The design currently is an 8 tap implementation, with the
multipliers and adders parts done in the HDL, VHDL, whilst the rest is standard
schematic entry. The whole thing can be easily modified (If you've got
Ispdesign Expert or the equivalent) for a different word width, order, or
even to change the response on the fly, by adding a simple I/O port, a
coefficient register ekcetera. Note, that we've not been able to test this
design out. Below is the basic structure of the Filter.
As we don't have any means to capture the schematic from IspDesignExpert, and convert it to a GIF that can be reasonably seen, you're going to have to download it and assess it for yourself. To tempt you, below is typical VHDL code for one of the multipliers. Fairly simple, Yes !
library ieee;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity mlt_add_c3 is
port(
clk: in std_logic;
X1: in std_logic_vector (9 downto 0);
Y1: in std_logic_vector (9 downto 0);
P1: out std_logic_vector (19 downto 0));
end;
architecture mlt_add_c3_arch of mlt_add_c1 is
begin
PROCESS (clk)
Variable C1:std_logic_vector (9 downto 0);
BEGIN
C1:=B"0001000001";
if (clk'event AND clk='1') then
P1<=C1 * (X1+Y1);
end if;
END PROCESS;
end mlt_add_c1_arch;
One thing that you have to do, is make sure that all the coefficients have relevant values. These can be had from some synthesis program, but make sure it can generate symmetric ones, for the group delay aspect.
Download Lattice 'ISPDesign Expert Starter' design file
After you've unzipped the above file to a separate directory, start up Ispdesign
Expert and click on OPEN PROJECT.Then find the DIGFIL.syn file, click on this,
and now play with the design. It may be possible to fit the design into a smaller
device. When this project was compiled, the environment was giving out all sorts
of messages. However it did create the .jed (JEDEC) file for downloading to the
chip. All that now needs to be done is possibly 'a long and tortuous
verification' (misquoted from John F. Wakerly's Excellent Textbook on Digital
Design)) that it actually works. No warranties at all for this design. Use at
your own risk.
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